As used herein, the term "semiconductor device" refers to a silicon chip or die containing circuitry, and the term "semi conductor device package" refers to the semi conductor device and associated packaging containing the chip, including leads such as for connecting to a socket or a circuit board, and internal connections, such as bond wires or solder bump (e.g., micro-bump) connections, of the chip to the leads.
In a typical modern semiconductor device package, a semiconductor die (device) is disposed within a package and is connected to conductive leads of the semiconductor device package (assembly) by means of bond wires or "solder bump" (micro-bump) connections. The connections to the semiconductor die are accomplished via metallic connection points or "bond pads" (I/O pads) disposed on a planar surface of the die, around the periphery (along the edges) thereof in a "peripheral area". The peripheral area is a ring-shaped area on the surface of the die, essentially a narrow band between the edges of the die and the "interior area" of the die. The conductive leads of the semiconductor device package may be provided by a leadframe, such as in a molded plastic or TAB (Tape Automated Bonding) semi conductor device package, or by printed traces, such as in a ceramic or overmolded printed circuit board package. The conductive leads approach the semiconductor die within the semi conductor device package in a generally radial pattern. They may also approach the die in parallel ranks, from one or more edges of the die.
Typically, a leadframe is stamped (or etched) from a sheet (foil) of conductive material, simultaneously forming all of the conductive leads of the leadframe. Often, the leadframe is held together by sacrificial "bridges" between the leads, which are removed after the leadframe is assembled to a die and a package body is formed. The leads are then effectively separate. However, by virtue of their common mounting within a package body, they continue to behave, in many respects, as a unit.
As the circuitry on a die operates, it dissipates power and heats up. Often, there is a mismatch between the thermal coefficients of expansion (TCE) of a semiconductor die and the leadframe (and package body) to which it is attached. This is especially troublesome where solder bump (micro-bump) connections are used to connect the die to the leadframe. (It is assumed that the heating of the die as it operates is fairly uniform). The die expands about its "centroid" (center of mass) as temperature rises, as do the leadframe and package body. However, the die expands at a different rate than the leadframe and package body, causing a great deal of mechanical stress at the interface between the leadframe and the bond pads (the solder bump connections). This stress creates a tendency of the bond pads to tear away from the die.
On any thermally expanding body, the further a point on the body is from the centroid, the greater the absolute distance it travels (displaces) during expansion. Since semiconductor dies are typically rectangularly shaped and the bond pads are typically disposed along the edges of the rectangular shape (in the peripheral area), the bond pads undergo a fairly large absolute displacement as compared to points located closer to the center of the die. Any bond pads located at the corners of the die, being furthest from the centroid, undergo the greatest displacement during thermal expansion. As a consequence of the absolute thermal displacements that any two different points undergo on the surface of the die, they undergo differential thermal displacements relative to one another. The further from one another that any two points on the surface of an expanding die are, the greater the differential thermal displacement between them. The leadframe and package body combination also expands about its centroid, albeit at a different rate. The center of expansion of the leadframe/package body combination is generally located fairly close to the centroid of the die, since the die is the heat source which causes the expansion. As a result, any differential thermal displacement causing mechanical stress at the bond pads of a semiconductor device is greatest at the corners of the die. The common practice of disposing bond pads along the edges of the die, therefore, would seem to create the worst possible circumstances from the point of view of thermal expansion.
Although the thermal expansion problem is most severe with micro-bump (solder bump) connections to a relatively rigid leadframe assembly, the same expansion characteristics apply to the die and leadframe/package body even if bond wires are used to connect the bond pads on the die to the leadframe. While bond wire connections are considerably more flexible and resilient than are solder bump connections, thermal flexing of bond wire connections can create long-term reliability problems.
One of the most significant reasons that bond pads are typically disposed about the edges (periphery) of a die is that the peripheral location of bond pads permits a relatively large number of connections to the die without causing connections (e.g., bond wires) to cross over one another. Current trends are towards providing smaller bond pads so that even greater numbers of I/O (and power) connections to the die may be accommodated. Unfortunately, these smaller bond pads are even more fragile than "ordinary" (larger) size bond pads, making such techniques even more prone to thermal stress problems.
Another problem with locating bond pads along the periphery of a die is that many of the connections are made to circuitry that lies well within the interior area of the die, requiring that the signals to and from that circuitry (and, in some cases, power to the circuitry) travel a relatively great distance within the die along the die's minute wiring structures (conductive lines) before they reach the bond pad connection. Hence, a "pad buffer" circuit is usually provided at or near a bond pad associated with an output signal to buffer the output signal at the bond pad. These factors can contribute to timing "skew", or differences in signal timing due to different wiring delays, particularly for very high speed circuits, which presents additional challenges to the circuit designer. The wiring structures (interconnections, or conductive lines) on the die are extremely small and exhibit relatively high (i.e., non-trivial) resistance. Even a tiny bond wire is a massive conductor compared to the relatively tiny interconnection lines on a die.
Power distribution to the chip is also hampered to some degree by the location of bond pads in the peripheral area. Circuits located close to the centerline (centrally located circuits) of the die receive power from the pads at the periphery of the die, usually along a branched "bus" structure formed in the wiring layers of the die. Power is distributed to other circuits between the pads and the centrally located circuits before it reaches the center of the die. While the power "bus" structure is typically routed in a fairly direct fashion, some branches of the power distribution bus can become fairly tortuous in reaching certain circuits. Many circuits located within the interior area of the die, particularly centrally located circuits, may receive power along a wiring path the length of which is greater than one half of the distance across the die. As a result, line losses and electrical noise problems may be experienced by those circuits which are most distant from the power distribution (bond) pads, particularly the centrally located circuits.
In order to minimize such line losses and electrical noise, it is common practice to provide multiple bond pads distributed about the periphery of the die for each power supply voltage. However, this does not solve the problem of the length of the power distribution path in the internal wiring layers of a die required to reach centrally located circuits.
Attention is directed to the following U.S. Patents, incorporated herein by reference, and of general interest with respect to leadframe-type semi conductor device packages and methods for manufacture thereof: U.S. Pat. No. 4,701,999 issued Oct. 27, 1987 to Palmer, U.S. Pat. No. 4,774,635 issued Sep. 27, 1988 to Greenberg et al., U.S. Pat. No. 4,894,704 issued Jan. 16, 1990 to Endo, U.S. Pat. No. 4,897,602 issued Jan. 30, 1990 to Lin et al., and U.S. Pat. No. 5,051,813 issued Sep. 24, 1991 to Schneider et al.
Attention is further directed to the following U.S. Patents, incorporated herein by reference, and of general interest with respect to micro-bump (e.g., solder bump) bonding: U.S. Pat. No. 3,429,040 issued Feb. 25, 1969 to Miller, U.S. Pat. No. 3,811,186 issued May 21, 1974 to Larnerd et al., U.S. Pat. No. 3,871,014 issued Mar. 11, 1975 to King et al., U.S. Pat. No. 3,984,860 issued Oct. 5, 1976 to Logue, U.S. Pat. No. 4,190,855 issued Feb. 26, 1980 to Inoue, U.S. Pat. No. 4,772,936 issued Sep. 20, 1988 to Reding et al., U.S. Pat. No. 4,803,546 issued Feb. 7, 1989 to Sugimoto et al., U.S. Pat. No. 4,825,284 issued Apr. 25, 1989 to Soga et al., U.S. Pat. No. 4,926,241 issued May 15, 1990 to Carey, and U.S. Pat. No. 4,970,575 issued Nov. 13, 1990 to Soga et al.
Other information relating to microbump bonding techniques may be found in Japanese Patent number 61-145838A issued on Jul. 3, 1986 to Kishio Yokouchi, and in "LED Array Modules by New Technology Microbump Bonding Method," by Hatada, Fujimoto, Ochi, and Ishida, IEEE Trans. Comp., Hybrids, and Manuf. Tech., Volume 13 no. 3, Sep. 1990, incorporated by reference herein.